Implementation of Power Gating Technique in Cmos Full Adder Cell to Reduce Leakage Power and Ground Bounce Noise for Mobile Application

Adder is the paramount circuit for many complex arithmetic operations. The adder cells mainly focus on reduction of power and increasing of speed. For mobile applications, designers work within a limited leakage power specification in order to meet good battery life. The designers apart from leveling of leakage current to ensure correct circuit operation also focuses on minimization of power dissipation. The power reduction must be achieved without comprising performance which makes it hard to reduce leakage current during normal operation of mobile. Power Gating is one such well known technique where a sleep transistor is added between actual ground rail and circuit ground. The device is turned off during sleep mode to cut-off the leakage path. This technique results in a substantial reduction in leakage at a minimal impact on performance. This paper will focus on reducing sub threshold leakage power consumption and ground bounce noise during the sleep to active mode transition. In the present paper we will propose low leakage 1 bit CMOS full adder circuit in 90nm technology with supply voltage of 1V. We will perform analysis and simulation of various parameters such as standby leakage power, active power, ground bounce noise and propagation delay using Cadence Spectre 90nm standard CMOS technology.